TESTABILITY GUIDELINES

For The Design Of

PRINTED CIRCUIT BOARDS

 

 

4.0 MECHANICAL RULES FOR TESTABILITY

4.1 GENERAL

4.1.1

 At least one test point must be made available for every electrical net, including Boundary Scan and/or Nand Tree pins.

4.1.2

 Usable test points may be any of the following.

Soldered lead of a through hole component.

Open hole for a through hole component when the component is not installed.

Solder filled via.

Open via hole when via is not to be filled with solder.

Test pad,  an area that is connected to a conductor trace and is designed to be a test point.

Finger edge connectors.

Boards designed and or manufactured with open component holes or open vias usually will not hold vacuum and require a test fixture with an overclamp. This adds to the expense and complexity of the test fixture.

4.1.3

 Do not cover any test point with solder mask. A test point is no longer usable once covered by solder mask.

4.1.4

 To aid in the fixture registration of all test points, two tooling holes, typically 0.125 inch (3.175 mm) + .000, - .003 in diameter, should be provided. The holes should be on a diagonal axis of the board. All tooling holes should be non-plated to insure correct dimensions.

4.1.5

 Test points should not be located less than 0.125 inch (3.175 mm) from the perimeter of the board or within 0.125 inch (3.175 mm) of the tooling holes.

4.1.6

 All components and connectors should be mounted on the topside whenever possible. This is especially true for those components that have a high profile. Bottom mounted components may require milling of the fixture probe plate to avoid interference with the component. This in turn causes the loss of nearby test points.

4.2 VIAS and TEST PADS

4.2.1

 Ideally, the printed circuit board will have 100% of the test points accessible from the bottom side. This may require that nets that exist only on the board topside, be brought to the bottom side using a via. It may also require that a test pad be added for nets that only exist on the board bottom side. Board designs that do contain test points that are only accessible from the topside will require a clamshell style test fixture. This will add to the expense of the test fixture.

4.2.2

 Avoid placing vias under components whenever possible. The possibility exists that the vias may trap flux and solder, causing shorts under the component.

4.2.3

 Provide multiple test points for power and ground nets. Ideally there should be at least one test point for every two devices on the power and ground nets.

4.2.4

 Test pads and vias should have a diameter of 0.030 inches (0.762 mm), with a minimum of 0.025 inches (0.635 mm). Most fixture manufacturers can reliably work with targets above 0.025 inches.

4.2.5

 The most desirable spacing of test points is on 0.100 inch (2.54 mm) centers. The next preferred spacing is 0.075 inch (1.9mm) centers. The least preferred spacing is 0.050 inch (1.27 mm) centers and is to be avoided if possible. The use of 50 mil probes add to fixture expense and may cause up to 3 misses per 1000 probes while testing.

 

Copyright © 1998-2000 Test Software Systems, Inc.
Last modified: January 07, 2004