9.0 SPECIAL DEVICES
| To inhibit PALS, GALS and FPGA’s while testing other devices, two
pins or functions should be provided within the devices. One pin should place all outputs
in the tri-state mode and one pin should reset all outputs and internal logic to a known
state. This will allow test vector creation software properly initialize internal circuits
and maximize fault coverage. If two pins are not available for this criterion, multiple
pins (used in the design) can be provided to serve the same purpose. The pins are at the
discretion of the design engineer, but must be provided to test engineering before test
program is developed. All programmable devices should be programmed before testing. |
| Batteries should have a removable jumper to disconnect it from the
circuit. If this is not possible, then the battery should be installed after testing. |
| When in-system programming of PLD’s and flash memory is required.
ALL driving signals to the devices must be tri-statable, to prevent driver failures due to
long burst times. |
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