1.0 Introduction

2.0 Scope

3.0 Overview

4.0 Mechanical Rules for Testability
     4.1 General
     4.2 Vias and Test Pads

5.0 Electrical Rules for Testability
     5.1 Testing Methods
     5.2 Analog Testing
     5.3 Digital Testing
     5.4 Inhibits
     5.5 Disabling
     5.6 Resets and Presets

6.0 Requirements for Testability
     6.1 Resets and Presets
     6.2 Initialization
     6.3 Control Lines
     6.4 Microproccesor Control
     6.5 Tri-Statable Devices
     6.6 Device Isolation

7.0 Component Interconnects
     7.1 Bussed Lines
     7.2 Feedback Loops
     7.3 Wired ORs
     7.4 Data Inputs
     7.5 Spares
     7.6 Power and Ground Pins
     7.7 160 Series Counters

8.0 Board Clocks
     8.1 Control Clocks
     8.2 Multiple Clocks
     8.3 Independent Clock Control

9.0 Special Devices
     9.1 PALS, GALS and FPGA’s
     9.2 Batteries
     9.3 ISP Devices and FLASH Memory

Appendix A
     Fig. 1: Sequential Device Control & Isolation
     Fig. 2: Feedback Loops
     Fig. 3: Data Inputs
     Fig. 4: Clocks (On Board)

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Test Software Systems, Inc.