| From your design entry tool, output the design as EDF, EDIF, SEDIF, PLD, SXNF, XNF, or
XTF file. Note that the PLD format is available only for XC7300 and XC9500 device families
only. In the DESIGN MANAGER, open an existing project file or create a new project file
into which to import your logic design.
Select Design --> Implement
If you wish, you can choose a different target device in which to implement your
design. The initial target device is specified in the input design or when you create a
new implementation revision.
Select an option template to specify implementation/configuration options. You can use
the default template, an existing template, or define a new template.
Process your design and create the Timing Simulation Files and the Device Programming
file. To do this,
In the Implementation Window, Click OPTIONS. From there, select
"Produce Timing Simulation Data" and "Produce Configuration Data."
Select EDIT TEMPLATE --> Simulator. There are three TABS to choose from.
Select EDIF. Deselect <Retain Hierarchy in netlist>.
This allows Design Manager to complete a Flattened EDIF Netlist.
Review the design reports to verify that your design fits within the target device and
that your timing requirements are met. If they are not met, then reprocess your design,
and either change your logic design, choose a different target device, package or speed
grade, or define a different set of implementation options.
The flattened netlist file is in the following location:
<working dir.>\<version dir.>\<revision dir.>\time_sim.edn |
